Referring to FIG. 1, a flash memory cell 100 of a flash memory device includes a tunnel dielectric structure 102 typically comprised of silicon dioxide (SiO2) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure 102 is disposed on a semiconductor substrate or a p-well 103. In addition, a floating gate structure 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure 102. A dielectric structure 106, typically comprised of silicon dioxide (SiO2), is disposed over the floating gate structure 104. A control gate structure 108, comprised of a conductive material, is disposed over the dielectric structure 106.
A drain bit line junction 110 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area 112 of the semiconductor substrate or p-well 103 toward a left sidewall of the floating gate structure 104 in FIG. 1. A source bit line junction 114 that is doped with the junction dopant is formed within the active device area 112 of the semiconductor substrate or p-well 106 toward a right sidewall of the floating gate structure 104 of FIG. 1.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or tunneled out of the floating gate structure 104. Such variation of the amount of charge carriers within the floating gate structure 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology.
For example, during programming of the flash memory cell 100 that is an N-channel flash memory cell, electrons are injected into the floating gate structure 104 to increase the threshold voltage of the flash memory cell 100. Alternatively, during erasing of the N-channel flash memory cell 100, electrons are pulled out of the floating gate structure 104 to the substrate or p-well 103 to decrease the threshold voltage of the flash memory cell 100.
FIG. 2 illustrates a circuit diagram representation of the flash memory cell 100 of FIG. 1 including a control gate terminal 120 coupled to the control gate structure 108, a drain terminal 122 coupled to the drain bit line junction 110, a source terminal 124 coupled to the source bit line junction 114, and a substrate or p-well terminal 126 coupled to the substrate or p-well 103. FIG. 3 illustrates an electrically erasable and programmable memory device 130 comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology. Referring to FIG. 3, the array of flash memory cells 130 includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell 100 of FIGS. 1 and 2.
The array of flash memory cells 130 of FIG. 3 is illustrated with two columns and two rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells.
Further referring to FIG. 3, in the array of flash memory cells 130 comprising an electrically erasable and programmable memory device, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In FIG. 3, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line 132, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line 134.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In FIG. 3, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line 136, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line 138. Further referring to FIG. 3, the source terminal of all flash memory cells of the array 130 are coupled together to a source voltage Vss, and the substrate or p-well terminal of all flash memory cells of the array 130 are coupled together to a substrate voltage VSUB.
Referring to FIG. 4, a flash memory device comprised of an array of flash memory cells as illustrated in FIG. 3 for example is fabricated on a semiconductor die of a semiconductor wafer 140. A plurality of semiconductor dies is manufactured on the semiconductor wafer 140. Each square area on the semiconductor wafer 140 of FIG. 4 represents one semiconductor die. More numerous semiconductor dies are typically fabricated on a semiconductor wafer than shown in FIG. 4 for clarity of illustration.
FIG. 5 illustrates an example semiconductor die 142 of FIG. 4 having a respective flash memory device comprised of a core array of core flash memory cells 144, such as the array 130 of FIG. 3 for example. In addition, the semiconductor die 142 includes periphery logic 146 for supporting operation of the core array 144, as known to one of ordinary skill in the art of flash memory technology.
CAM (content addressable memory) cells 148 are used within the periphery logic 146 for supporting operation of the core array 144, as known to one of ordinary skill in the art of flash memory technology. The CAM cells 148 typically are non-volatile memory cells, each implemented with a cross-section similar to the flash memory cell 100 of FIG. 1 for example.
One example application of the CAM cells 148 is for WP (write protect) functionality. The present invention is described in reference to WPCAM (write protect content addressable memory) cells used for WP functionality. However, the present invention may be used for implementing CAM (content addressable memory) cells used for other functionalities within the flash memory device, as would be apparent to one of ordinary skill in the art of flash memory technology from the description herein. Referring to FIG. 8, for WP functionality, a respective WPCAM cell is formed for each sector of the core array 144. Typically, the flash memory cells within the core array 144 are organized into sectors, as known to one of ordinary skill in the art of flash memory technology. Each of the sectors of the core array 144 is comprised of a corresponding group of word lines but share the same bit lines.
In FIG. 8, a first WPCAM cell 152 is formed for a first sector 162, a second WPCAM cell 154 is formed for a second sector 164, a third WPCAM cell 156 is formed for a third sector 166, and a fourth WPCAM cell 158 is formed for a fourth sector 168. The core array 144 is typically comprised of more numerous sectors, but four sectors and four WPCAM cells are illustrated in FIG. 8 for simplicity and clarity of illustration and description.
For WP functionality, each of the WPCAM cells 152, 154, 156, and 158 is programmed or erased to indicate whether a corresponding one of the sectors 162, 164, 166, or 168 is write protected. If a sector is write protected, the flash memory cells within that sector cannot be programmed or erased, but may be read. For example, when any of the sectors 162, 164, 166, or 168 is write protected, the corresponding one of the WPCAM cells 152, 154, 156, and 158 is programmed, and is erased otherwise. Thus, for determining whether any of the sectors 162, 164, 166, or 168 is write protected, the programmed or erased state is read from the corresponding one of the WPCAM cells 152, 154, 156, and 158.
FIG. 6 illustrates a block diagram of components of the periphery logic 146 for supporting such WP functionality with the WPCAM cells 148. A WPCAM margin circuitry 153 generates a gate voltage to be applied on a gate of a WPCAM cell during program or erase margining of one of the WPCAM cells 152, 154, 156, and 158. Program and erase margining of a CAM cell is known to one of ordinary skill in the art of flash memory technology.
In addition, a WPCAM gate voltage booster 155 generates a gate voltage to be applied on a gate of a WPCAM cell during reading of the programmed or erased state of one of the WPCAM cells 152, 154, 156, and 158. Furthermore, a WPCAM program circuitry 157 and a WPCAM erase circuitry 159 each generate a gate voltage to be applied on a gate of a WPCAM cell during programming or erasing, respectively, of one of the WPCAM cells 152, 154, 156, and 158.
A WPCAM gate voltage switch 160 selects a gate voltage from one of the gate voltage sources 153, 155, 157, and 159 depending on the current WPCAM operation to be performed as indicated by WP operation mode signals derived from external data as input by a user. The user inputs data to indicate whether a WPCAM cell is desired to be margined, read, programmed, or erased.
The address of one of the WPCAM cells 152, 154, 156, and 158 of interest is indicated from the sector address within an address sequencer 161. FIG. 9 shows an example address sequencer 161 including a first group of seven bit buffers A[6:0] 167 for indicating a Y-address of a flash memory cell within the core array 144, a second group of eight bit buffers A[14:7] 169 for indicating an X-address of a flash memory cell within the core array 144, and a third group of five bit buffers A[19:15] 170 for indicating a sector address of a flash memory cell within the core array 144.
Since each of the WPCAM cells 152, 154, 156, and 158 corresponds to one of the sectors of the core array 144, the sector address bits A[19:15] are used by a WPCAM location decoder 172 for selecting one of the WPCAM cells 152, 154, 156, and 158 of interest. The gate voltage as selected by the WPCAM gate voltage switch 160 is applied on the gate of such a WPCAM cell of interest as selected by the WPCAM location decoder 172. In addition, a WPCAM drain voltage generator 174 generates a drain voltage to be applied on a drain of such a WPCAM cell of interest for a programming or erasing operation. The WPCAM drain voltage generator 174 generates a proper level of such a drain voltage depending on the current WPCAM operation indicated by the WP operation mode signals (i.e., for programming or erasing).
With the gate voltage for reading applied on the WPCAM cell of interest from the WPCAM gate booster 155, the drain of the WPCAM cell of interest is coupled to a weak pull-up circuitry 177. The drain is pulled down to the ground voltage to indicate an erased WPCAM cell or is pulled up to a positive rail voltage to indicate a programmed WPCAM cell. A WPSB (write protect state bit) indicates such a programmed or erased state of the WPCAM cell of interest. If the WPSB indicates that the WPCAM cell of interest is programmed, the back-end state machine 176 disables programming or erasing of any flash memory cell within a sector corresponding to the WPCAM cell of interest. When the WPCAM cell of interest is programmed, the sector corresponding to the WPCAM cell of interest is write-protected.
On the other hand, if the WPSB indicates that the WPCAM cell of interest is erased, the back-end state machine generates a control signal for programming or erasing a flash memory cell within the sector corresponding to the WPCAM cell of interest. In that case, the sector corresponding to the WPCAM cell of interest is not write-protected.
Such WPCAM cells 148 and such write-protect functionality are known to one of ordinary skill in the art of flash memory technology. In addition, implementation of the components 148, 153, 155, 157, 159, 160, 161, 172, 174, 176, and 177 of FIG. 6 are known to one of ordinary skill in the art of flash memory technology.
FIG. 7 illustrates additional components of the periphery logic 146 for supporting use of the core array of flash memory cells 144. A program circuitry 182 generates programming voltages to be applied on the gate and the drain of a core flash memory cell within the core array 144. Similarly, an erase circuitry 184 generates erasing voltages to be applied on the gate and the drain of a core flash memory cell within the core array 144. In addition, a read/verify circuitry 186 generates the reading voltage to be applied on the gate of a core flash memory cell within the core array 144. Furthermore, the read/verify circuitry 186 couples the drain of the core flash memory cell to a cascode sense amplifier for determining the programmed or erased state of the core flash memory cell.
The address sequencer 161 indicates the address of a core flash memory cell of interest within the core array 144 to be programmed, erased, or read. Referring to FIGS. 7 and 9, a Y-decoder 190 decodes the Y-address bits A[6:0] from the address sequencer 161 for selecting the bit-line of the core flash memory cell of interest within the core array 144. Similarly, an X-decoder 188 decodes the X-address bits A[14:7] from the address sequencer 161 for selecting the word-line of the core flash memory cell of interest within the core array 144.
Referring to FIGS. 7 and 8, the X-decoder 188 includes a plurality of X-decoder units, each for selecting a word-line for a core flash memory cell within a respective sector. In FIG. 8, a first X-decoder unit 192 selects a word-line for a core flash memory cell within the first sector 162, and a second X-decoder unit 194 selects a word-line for a core flash memory cell within the second sector 164. Similarly, a third X-decoder unit 196 selects a word-line for a core flash memory cell within the third sector 166, and a fourth X-decoder unit 198 selects a word-line for a core flash memory cell within the fourth sector 168. On the other hand, the Y-decoder 190 selects the bit line for a core flash memory cell in any of the sectors 162, 164, 166, and 168 that share the bit lines.
Referring to FIG. 7, each of a plurality of sector switches 200 gates a negative erasing gate voltage from the erase circuitry for a respective one of the sectors 162, 164, 166, and 168. In addition, a state decoder 202 decodes data from I/O pads to determine the mode of operation to be performed on the core array 144.
If such data from the I/O pads indicates programming a core flash memory cell of interest within the core array 144, the back-end state machine 176 generates a program pulse to control the program circuitry 182 to generate programming voltages. The address sequencer 161 indicates the address of the core flash memory cell of interest within the core array 144 to be programmed. Such an address may be input into the address sequencer via address pads by an external user.
The X-decoder 188 decodes the X-address bits A[14:7] from the address sequencer 161 and applies the programming gate voltage from the program circuitry 182 on a selected word line for the core flash memory cell of interest within the core array 144. Similarly, the Y-decoder 190 decodes the Y-address bits A[6:0] from the address sequencer 161 and applies the programming drain voltage from the program circuitry 182 on a selected bit line for the core flash memory cell of interest. In this manner, the core flash memory cell of interest within the core array 144 is programmed.
On the other hand, if the data from the I/O pads into the state decoder 202 indicates erasing a sector of core flash memory cells of interest within the core array 144, the back-end state machine 176 generates an erase pulse to control the erase circuitry 184 to generate erasing voltages. For the erasing operation, core flash memory cells are erased a sector at a time. The address sequencer 161 indicates the sector address of the sector of interest within the core array 144 to be erased. Such a sector address may be input into the address sequencer via address pads by an external user.
The X-decoder 188 applies the erasing gate voltage from the erase circuitry 184 on the word lines for the selected sector of interest within the core array 144. Similarly, the Y-decoder 190 applies the erasing drain voltage from the erase circuitry 184 on the bit lines for the sector of interest. In this manner, the core flash memory cells within the sector of interest are erased.
In addition, for reading the core flash memory cell of interest within the core array 144, the X-decoder 188 applies the reading gate voltage from the read/verify circuitry 186 on a selected word line for the core flash memory cell of interest. Similarly, the Y-decoder 190 couples a cascode sense amplifier within the read/verify circuitry 186 to a selected bit line for the core flash memory cell of interest. The cascode sense amplifier within the read/verify circuitry 186 then determines the programmed or erased state of the core flash memory cell of interest for the back-end state machine 176.
Such programming, erasing, and reading operations for the flash memory cells within the core array 144 are known to one of ordinary skill in the art of flash memory technology. In addition, implementation of the components 182, 184, 186, 188, 190, 200, and 202 of FIG. 7 are known to one of ordinary skill in the art of flash memory technology.
Referring to FIGS. 6 and 7, in the prior art, the WPCAM cells 148 are fabricated as separate flash memory cells from the core array 144. In the prior art, the size dimensions and the material comprising the structures of the flash memory cells 152, 154, 156, 158 of the WPCAM cells 148 are designed to be different from the core flash memory cells within the core array 144.
The WPCAM cells 148 are used for storing write protect information for each sector of the core array 144. On the other hand, the flash memory cells within the core array 144 are used with numerous cycles of programming and erasing. Thus, the size dimensions and the material of the WPCAM cells 148 are designed for optimizing charge retention, whereas, the size dimensions and the material of the flash memory cells within the core array 144 are designed for optimized reliability for millions of cycles of programming and erasing.
Because of such differences between the WPCAM cells 148 and the flash memory cells within the core array 144, separate circuitry within the periphery logic is used for supporting operation of the WPCAM cells 148 and the flash memory cells within the core array 144. The components 153, 155, 157, 159, 161, 172, 174, and 177 of FIG. 6 are formed within the periphery logic 146 for supporting operation of the WPCAM cells 148, whereas, the components 182, 184, 186, 188, 190, 200, and 202 of FIG. 7 are formed within the periphery logic 146 for supporting operation of the flash memory cells within the core array 144.
Such numerous components of the prior art for supporting operation of the WPCAM cells 148 are disadvantageous because of added complexity and area occupied by the flash memory device. In addition, the additional WPCAM cells themselves that are designed to be relatively large for optimized charge retention occupy additional area. Nevertheless, WPCAM cells for WP functionality are desired for the flash memory device.
Thus, a mechanism is desired for providing CAM cells within the flash memory device with a minimized number of components for supporting operation of the CAM cells and with minimized area for the die of the flash memory device.